PCB Layout Experience Sharing Helps You Improve Work Efficiency
As one of the PCB design services, PCB Layout is a technical activity and an experiential activity. Learning something useful can often be very rewarding. Next, I would like to share with you some PCB Layout experiences with our engineers. Holp it's helpful for you.
10 Tips of PCB Layout Experience
1. Please Place The ESD Protection Devices Near The Terminals
In other words, the ESD protection device should be placed near the input and output ports of the PCB.
For example, the HDMI, USB, VGA, power, lighting and other interfaces of our laptops are the places where the human body can easily reach, so you need to add some electrostatic protection devices when PCB layout.
Close to the port is to release the electrostatically released energy directly to the ground at the port, because if it is at the chip end, some devices in the board may be affected. The simple understanding is to "strangle static electricity in the cradle".
2. The Distance Between The Crystal and The Device Needs To be Slightly Larger.
First of all, it is necessary to pay attention to the fact that the crystal will cause the frequency deviation to increase at the temperature, so pay attention to the relevant description of the device when the crystal is laid out. If there is no description, it is placed near the main chip by default, but if there is a description (generally a heating device), It will tell you how far away the device is. If so, you can ground it at a single point, separate the ground of the crystal from other areas, and finally ground it in a small area.
The frequency of the signal output by the crystal is very high, so if it is coupled to a certain signal and conducted out, it may cause electromagnetic compatibility problems. Therefore, do not run a trace near the crystal. If you want to go, you need to route the trace to the crystal ground. wrap up.
3. The Ground and Ground Vias of The Clock Line CLK.
The land parcel is a supplementary icing on the cake. The most essential thing is to require a complete ground plane.
Too little or too small ground coverage is not conducive to signal backflow. The signal backflow must meet the minimum impedance requirements. If there is a problem in the package ground that it is difficult to punch holes, this will cause the ground impedance to increase. Parasitic parameters), it is better to not cover the ground, and maintain a complete ground plane layer.
It is best not to cross-layer clock routing. It is feasible to cross-layer but refer to one layer at the same time (for example, to route on layers 1 and 3, refer to 2 layers of ground; or routed on layers 1 and 4 but The 2nd and 3rd layers are best ground referenced, and the 3rd layer is not divided between ground and power).
4. Sensitive Signal Interference Problems.
Such as clocks, important signal lines, close to crystals, and inductors may cause crosstalk interference problems.
To solve this problem, if the board space is sufficient, you can pull as far as you can.
If board space is not enough, consider multi-layer board design, or increase the width of the ground wire as much as possible.
5. Power Cables Are Too Dense.
The power supply wiring is too thin and the power supply wiring vias are too dense, resulting in poor ground connection.
The problem of too-thin power supply traces is that when the backload requires extremely high current, it is an AC change in an instant, so a voltage drop occurs on the parasitic inductance of the thin trace, causing the demand-side voltage to be reduced by the power supply. Voltage drops across parasitic inductances can cause problems at this time.
The reason for the vias being too dense is that the current carried by each via is constant, but when a large current is required, multiple vias need to be driven in parallel. At this time, if the vias are connected, it may cause division (see how much hole).
6. The Number of Vias on The Bottom of The Device.
Too few vias will not only affect the signal reflow of the chip but also not conducive to the heat dissipation of the chip.
Because the size of the device is now very small, the contact area with the Printed circuit board is reduced, which in turn causes the thermal resistance to increase. Therefore, we use vias to increase heat dissipation capabilities, but for chips with relatively large power consumption. Need a heat sink.
The ground reflow is proposed for high-speed signals. The ground loop should be kept to a minimum area and the ground trace area should be kept as large as possible, but the largest area on the circuit board is the ground reference layer, so we hit Vias facilitate backflow.
7.About PCB Antenna Layout
In the process of the PCB layout, our engineer recommend you to increase the area of the forbidden area around the antenna. The normal minimum is 3mm. Increasing the spacing is conducive to the performance of the antenna.
8. Pay Attention To the Position of The Dividing Line.
Please place the vias close to the dividing line. The split line will cause the reflow path on the PCB to become longer, which is not desirable for high-speed signals, so it is necessary to add vias in the cross-segment area to make the signal reflow through the vias.
9. Please add teardrops to the wiring of the connection terminal.
Otherwise, the impedance discontinuity will become worse. The purpose of increasing teardrops is to make the right of the trace gradually thinner or the game thicker, and to increase continuity, not directly change.
10. Don't punch through the key signals.
You can sacrifice some unimportant signal traces to make the key signal traces completely.
That's all for this article. Do you have any good PCB Layout experience and skills? Welcome to leave a message or comment, your support is the biggest motivation for our creative update.
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